A wide variety of audio formats at varying levels of specification and fidelity can be recorded on digital versatile disks (DVD""s). One specification, known as DVD-Audio, supports formats such as Dolby Digital and digital theater systems (DTS) to provide multiple channels of audio for surround-sound effects.
PCM or xe2x80x9cPulse-Coded-Modulationxe2x80x9d is the audio format standard for compact discs (CD""s) and it is available on many DVD-Video""s. DVD-Audio supports a significantly higher quality of PCM audio than is possible on CD or DVD-Video. Full multi-channel surround sound can be recorded in the PCM format to create a sound field with the ambience and fullness of a live performance. DVD-Audio PCM can be recorded with a range of frequencies that are more than four times that of a CD, thereby providing fidelity and dynamic range that is not possible on a CD.
With PCM, the ability to accurately represent an analog signal in digital form is mainly dependent upon the xe2x80x9csample sizexe2x80x9d and xe2x80x9csampling rate.xe2x80x9d The combination of sample size and rate are commonly represented as two numbers such as 24/96 meaning a 24-bit sample size taken at a rate of 96,000 samples per second.
Sample Size or xe2x80x9cQuantizationxe2x80x9d is the number of data bits used to represent the analog audio signal each time it is sampled when being converted from an analog signal to a digital form. A larger number of bits allow the amplitude of the audio signal to be represented more accurately.
Sampling Rate or Sampling Frequency is the number of samples taken per second when converting the analog signal to digital. A higher xe2x80x9csampling ratexe2x80x9d allows for higher frequencies to represented.
The greater the number of bits used for sample size and the greater the sample rate, the more accurately the analog signal can be represented in digital form. With a sample size of 24 bits and a sample rate of 192 KHz (24/192), DVD-Audio is capable of recording an audio signal with a frequency range of 0 to 96 KHz with a dynamic range of 144 dB.
In multi-channel recordings, the DVD-Audio PCM specification allows each track to be recorded with different sampling rates and sample sizes. For example, 24/96 can be used for the front channels and 16/48 for the rear. The DVD Audio specification currently mandates two channels of 192 kHz/24 bit and up to six channels of 96 kHz/24 bit. Other sample rates and word lengths can also be used such as 44.1, 48 or 88.2 kHz at either 16, 20 or 24 bits for one to six channels on any given program or track.
Additionally, combinations of sample rates and word lengths could be used. For example, a 5-channel music mix could be produced with the front three channels, left, center, and right delivered at 96-kHz/24 bit, and the left and right surround channels delivered at 48-kHz/16 bit.
Direct Stream Digital (DSD) is another digital encoding format used to record Super Audio CD (SACD), which are high resolution multi-channel digital audio recordings albums. DSD samples an audio signal at a fixed rate (frequency) just as in the PCM method. However, instead of recording the volume or amplitude as an absolute number, as in PCM, the DSD method measures and records how much the volume has changed since the last measurement. If the signal is sampled fast enough, the amount of change since the previous sample is very small, and the change in signal strength can be represented with one bit.
One component in DVD players is a digital to analog converter (DAC) that converts digital signals to analog signals for output to analog devices, such as audio speakers. While a single DAC can process multiple signals, the signals must all have the same sample rate. Thus, the various channels must all be converted to the same sample rate before being input to the DAC.
It is therefore desirable to provide an apparatus that is capable of processing D/A conversions for multiple channels with input signals having two or more different sample rates.
In accordance with the present invention, multiple digital input signals sampled at different rates are converted to analog signals using a different digital to analog converter for each digital input signal. A set of sample rate signals indicating the sampling rate for each digital input signal are used to route each digital input signal, along with a corresponding clock signal, to a digital to analog converter (DAC). A clock error signal controls the power-up of each DAC. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.
In one embodiment, a first digital to analog converter is coupled to receive a first clock signal and a first digital input signal corresponding to a first sample rate, and a second digital to analog converter is coupled to receive a second clock signal and a second digital input signal corresponding to a second sample rate.
One aspect of this embodiment includes a control router coupled to receive the first and second digital input signals, the first and second clock signals, and first and second control signals. The first and second control signals include an indicator of the sample rate of the first and second digital input signals. The control router is operable to route the first digital input signal and the first clock signal to the first digital to analog converter, and to route the second digital input signal and the second clock signal to the second digital to analog converter.
Another aspect of this embodiment includes a serial interface coupled to the first and second digital to analog converters, wherein the serial interface transmits the first digital input signal to the first digital to analog converter, and the second digital input signal to the second digital to analog converter.
Another aspect of this embodiment includes a plurality of digital to analog converters corresponding to the plurality of digital input signals. The control router transmits at least two of the plurality of digital input signals to the corresponding digital to analog converter, and the remaining plurality of digital input signals are input directly to the corresponding digital to analog converter.
In another embodiment, a control router receives the sample rate signals. Other control signals such as power down, power up, and reset, generated by a state machine for each sample rate, can also be input to the control router. A first and second DAC, and a serial interface are coupled to the control router and the serial interface transmits the digital input signals to the control router. The control router transmits the first and second clock signals and corresponding digital input signals to the first and second DACs, respectively.
One feature of an apparatus in accordance with the present invention is a master =clock that generates a master clock signal. A clock divider and ratio detector module determines a master clock mode based on the first and second clock signals, and the master clock signal. The clock divider and ratio detector also generates a first clock error signal to indicate whether the master clock mode has been determined for the first clock signal, and a second clock error signal to indicate whether the master clock mode has been determined for the second clock signal. An overall clock error signal can be determined based on the first clock error signal and the second clock error signal.
Another feature of an apparatus in accordance with the present invention is a first state machine coupled between the clock divider and ratio detector module and the control router. The first state machine generates at least one of the control signals based on the overall clock error signal and the frame clock for the first sample rate. The apparatus can also include a second state machine coupled between the clock divider and ratio detector module and the control router. The second state machine generates at least one of the control signals based on the overall clock error signal and the frame clock for the second sample rate.
In another embodiment, an apparatus in accordance with the present invention includes a plurality of digital to analog converters corresponding to the plurality of digital s input signals and the control router transmits each of the plurality of digital input signals to the corresponding digital to analog converter.
In yet another embodiment, a plurality of state machines corresponding to each sample rate, is included in the apparatus. Each state machine receives a clock error signal, and transmits the clock error signal to the control router to control operation of the plurality of digital to analog converters.
In certain embodiments of an apparatus in accordance with the present invention, the various components can be implemented as hardware circuitry, as software program instructions executable on a data processor, or a combination of hardware and software.
In another embodiment, a method for converting a plurality of digital input signals sampled at multiple sampling rates to analog signals in accordance with the present invention includes:
generating a clock error signal, wherein the clock error signal is based on two or more clock signals corresponding to different sampling rates, and
routing each of the digital input signals, and the clock signal corresponding to the sampling rate of the digital input signal, to one of a plurality of digital to analog converters, when the clock error signal is at a predetermined value.
In one embodiment of the method in accordance with the present invention, generating the clock error signal includes generating intermediate clock error signals corresponding to each of the different sample rates, wherein each of the intermediate clock error signals is based on the clock signal that corresponds to the sample rate, and generating the clock error signal based on the intermediate clock error signals.
In another embodiment of the method in accordance with the present invention, generating the clock error signal further comprises generating clock mode signals corresponding to each of the different sample rates, wherein each of the clock mode signals is based on the clock signal that corresponds to the sample rate, generating the clock error signal based on the clock mode signals.
In a further embodiment of the method in accordance with the present invention, generating the clock error signal further comprises generating clock wait signals corresponding to each of the different sample rates, wherein each of the clock wait signals is based on whether the clock signal that corresponds to the sample rate is rising, and generating the clock error signal based on the clock wait signals.
These and other embodiments of the invention are further described below with respect to the following figures.